To reduce fabrication costs of semiconductor devices, it is necessary to increase the level of integration of the semiconductor devices and minimize the number of fabricating steps. In the meantime, as portable electronic devices like cellular phones, camcorders, and game machines have become popular, a need for embedded memory logic (EML) semiconductor devices having both memories and logic circuits has been gradually increasing. In most such cases, the EML semiconductor devices incorporate DRAM elements as the memories for high-speed operations.
FIG. 1 is a cross-sectional view illustrating a method of fabricating a capacitor of a typical DRAM semiconductor device.
Referring to FIG. 1, a first interlayer dielectric layer (ILD) is formed on the semiconductor substrate 10. The first ILD is then patterned and etched to form a first interlayer dielectric pattern (ILD pattern) 20 with a first opening 25. The first opening 25 exposes a predetermined region of the semiconductor substrate 10. A conductive contact plug 30 is formed in the first opening 25 to contact the exposed region of the semiconductor substrate 10.
A second ILD is then formed on an entire surface of the semiconductor substrate including the contact plug 30. The second ILD is then patterned and etched to form a second ILD pattern 40 having a second opening 45. The second opening 45 exposes a top surface of the contact plug 30.
A lower electrode layer and a sacrificial layer (not shown) are formed on the entire surface of the semiconductor substrate including the second ILD pattern 40. Thereafter, an upper portion of the sacrificial layer and the lower electrode layer are etched to expose a top surface of the second ILD pattern 40 and leave a lower electrode 50 and a sacrificial pattern (not shown) filling the second opening 45. The sacrificial pattern is then removed to expose an inner wall of the lower electrode 50.
A dielectric layer 60 and an upper electrode layer are then sequentially formed on an entire surface of the semiconductor substrate including the exposed lower electrode 50. The upper electrode layer is then patterned and etched to expose a portion of a top surface of the dielectric layer 60 and form an upper electrode 70 that fills the remaining portion of the second opening 45.
Fabrication of a DRAM capacitor according to the conventional method comprises repeatedly performing a series of photolithographic and etching processes in order to form the first opening 25, the second opening 45, and the upper electrode 70. The present invention is directed to a method for decreasing the number of these photolithographic and etching processes to simplify the process and reduce the fabrication costs associated with producing such semiconductor devices.
In addition, a DRAM cell capacitor typically includes a lower electrode 50 having a height h1 of at least about 10,000Å to realize highly integrated devices and secure a sufficient capacitance. However, as a result of the relatively extreme height h1 of the lower electrode 50, DRAM fabrication processes are generally not compatible with those of more planar logic circuits. As a result, attempts to combine these processes makes it difficult to simplify the fabrication of EML semiconductor devices, and this may actually increase the fabrication costs and complexity.